The present invention relates to a semiconductor device, and more particularly to an input circuit of a semiconductor device that ensures stable operation.
A typical semiconductor device includes a signal transferring unit that receives and transfers a signal, and a signal processing unit that processes the signal transferred by the signal transferring unit according to a unique predetermined operation.
Typically, a signal processing unit is referred to as the core circuit of the semiconductor device, and as many devices as the current design and processing technology will allow are integrated in the core circuit.
The signal transferring unit is provided with an input circuit for transferring an external signal to the signal processing unit within a semiconductor device and an output circuit for outputting data transferred from the signal processing unit to outside.
In a semiconductor device, particularly in a semiconductor memory device, the input circuit typically receives an external address signal or data, and the input circuit transfers the external address signal or data to an internal memory core region. The output buffer outputs a data signal corresponding to the inputted address signal.
The input circuit that transfers the external data signal or address signal to the internal memory core region should perform an accurate buffering operation, since a semiconductor device can reliably operate only when accurate buffering is ensured.
FIG. 1 is a circuit diagram showing a conventional input circuit of a semiconductor device. In a typical semiconductor memory device, the input circuit has a differential amplifier structure. The configuration shown in FIG. 1 is an example of a DRAM, which is typical semiconductor memory device.
The circuit in FIG. 1 includes an input buffer 100 receiving input signals in and inb, a delaying circuit 200 delaying the output signal of the input buffer 100, a clock buffer 300 receiving clock signals CLK and CLKB, and a strobe & latch circuit 400 receiving the output of the delaying circuit 200 and the output signal of the clock buffer 300.
Generally, the input buffer 100 has a structure that differentially amplifies the input signals in and inb, and is a circuit receiving an external signal such as an address in a semiconductor memory device, a control signal, or the like.
The delaying circuit 200 is a circuit for adjusting the timing (i.e. a setup time or a hold time) used to synchronize the input signals in and inb (examples of the input signal being an address, a control signal, or the like) with a clock.
The clock buffer 300 is a circuit for receiving the system clock signals CLK and CLKB which are inputted from outside.
The strobe & latch circuit 400 is a strobe circuit for clock synchronization.
The input circuit in FIG. 1 has a differential input buffer structure for receiving a differential signal. Herein, the differential input refers to signals having opposite phases, such as clocks CLK and CLKB.
When the differential input (i.e. input signals in and inb) are inputted into the input buffer 100, the input buffer 100 differentially amplifies the input signals in and inb. The crossing point of this differential input (the point at which the signal in and the signal inb cross) is referred to as VIX.
Herein, the level of the crossing point VIX is typically a Vref level, e.g. VCC/2. However, there may be situations where the level of the crossing point VIX is not adjusted to the exact Vref level due to influences such as noise, etc.
Even in situations in which the crossing point VIX is higher or lower the Vref level, the reaction speed of the output signal must have a constant reaction speed or the input circuit will not have stable operation. However, when the input potential is low, a delay in the output signal will typically occur, and thus the setup time and the hold time vary a great deal. Therefore, the input circuit does not operate in a stable manner.
FIG. 2 is a graph illustrating variation in operation speed of the input buffer 100 according to variation in the input potentials of the input signals in and inb of FIG. 1. FIG. 1 also shows variation in the extent of delay ‘t’ according to the variation in the input potentials of the input signals in and inb is shown. Herein, ‘t’ is the time it takes for the input signals in and inb to be inputted into the input buffer 100 and then outputted from the input buffer 100. The variation pattern or of the amount of variation in ‘t’ may be different depending on the type of input buffer 100.
FIG. 3 shows an input buffer 100 having a differential amplifying structure that has the properties illustrated in FIG. 2.
Referring to FIG. 3, when an enable signal en has a high the input buffer 100 is enabled. A driving transistor 32 is turned on when the enabling signal has a high level to operate the input buffer 100. Herein, when the input buffer 100 is described as operating, the input buffer 100 compares and amplifies the levels of the input signals in and inb to output as a buffer output signal buf_out.
The enable signal en is input at a logic low level when the input buffer 100 is disabled and the driving transistor 32 is turned off. When the enable signal en is disabled, the input buffer 100 does not compare the input signals in and inb, and in this case the input buffer 100 outputs a constant high level buffer output signal buf_out since PMOS transistors 34 and 36 receive the enable signal en having the low level via their respective gates. Fixing the buffer output signal buf_out at a high level prevents the node that outputs the buffer output signal buf_out from being floated when the input buffer 100 is in the disabled state.
Referring again to FIG. 2, A period in FIG. 2 is a period in which the crossing point VIX is higher than the reference voltage level, and B period is a period in which the crossing point VIX is lower than the reference voltage level. When compared to the A period, the ‘t’ value of the B period is greater. As shown in FIG. 2, when the input levels of the input signals in and inb are low, the setup time and the hold time vary a large degree due to the delay of the output signal, and thus the input buffer does not operate in a stable manner.
Voltage differences Vgs between the gate and source of NMOS transistors N0 and N1 in FIG. 3 become lower than a threshold voltage Vth when the level of the input voltage of the input buffer lowers. Therefore, a period in which the NMOS transistors N0 and N1 are turned off is generated, and the input buffer does not operate normally. As a consequence, malfunctions occur in the semiconductor memory device.